For any system comprising various circuits, the production cost can be reduced and the signal transmission reliability can be enhanced by incorporating these circuits into a single chip, which is so-called as a system on a chip (SOC). The SOC is becoming a mainstream for circuit design.
The SOC design, however, has not been perfectly developed yet. Therefore, for most systems, several circuit blocks or chips associated with different functions are still included in the system configuration, and a circuit board is required to serve as a platform for integrating the circuit blocks or chips. As such, the signal transmission on the circuit board is significantly affected by the properties of the circuit board, which includes the material of data transmission traces, the length of traces, the width of traces, the uniformity of traces, the signal interaction between traces and the linearity of traces, etc. In addition, the performance of the entire system also highly depends on the signal transmission quality of the circuit board.
Therefore, the waveforms of signals generated by the circuit blocks or chips and transmitted via the traces of the circuit board are checked to see if they appear as expected. The waveform information also serves as an index to determine whether the system design is successful.
Currently, the testing procedures of the system include the tests for individual circuit blocks or chips before they are assembled to a circuit board, and the tests for the assembled circuit board. A test signal outputted from a verified source chip to a verified destination chip via traces of the circuit board is checked manually by way of an external measuring tool to realize the data transmission quality. From the detected waveforms, the signal variation degree resulting from signal reflection and interference can be realized so as to determine the data transmission quality.
As is understood, the manual detection of the test signal wastes lots of time and labor. Moreover, if the quality requirement on the data transmission between circuit blocks or chips is very high, each of the circuit boards would need to be checked one by one to assure a high data transmission quality. Under this circumstance, the spent time and labor would be tremendous.
A conventional method for checking the data transmission quality of a circuit board incorporating therein separate chips will be illustrated hereinafter with reference to FIGS. 1 and 2A˜2C. In FIG. 1, the circuit blocks and signals associated with the transmission quality test are shown. On the circuit board 10, a source chip 11 and a destination chip 12 are mounted. The source chip 11 outputs a test signal S1, which is transmitted to the destination chip 12 via a trace 13. The trace 13 is generally a metal conductive line made of copper foil.
In this prior art, the electric level of the test signal S1, after being transmitted to the destination chip 12, is likely to fluctuate during electric toggling due to signal reflection and interference. For example, superimposition of signals may occur. In addition, the trace 13 is considered as some kind of circuit impedance for signal transmission. If the circuit transmission impedance matching provided by the trace 13 is inferior, the waveform information detected by the external measuring tool will indicate significant electric level fluctuation of the test signal S1 during toggling.
FIGS. 2A˜2C show the waveforms of the test signal S1 detected in various stages, wherein the electric level of the test signal S1 is considered high when it is higher than a first reference level Hi, and considered low when it is lower than a second reference level Lo.
Please refer to FIG. 2A which shows the test signal S1 generated by the source chip 11 and having not been transmitted via the trace 13 yet. At this stage, the waveform of the test signal S1 during the toggling period Tr1 is as shown. Further, after the test signal S1 is transmitted via the trace 13 to the destination chip 12 through signal reflection and interference, the ideal superimposed waveform of the test signal S1 during the toggling period Tr2 is as shown in FIG. 2B, on the condition that the trace 13 forms an ideal circuit impedance matching for the signal transmission of the test signal S1. On the other hand, if the trace 13 forms an inferior circuit impedance matching for the signal transmission of the test signal S, the waveform of the test signal S1 will be as shown in FIG. 2C. That is, during the toggling period Tr3, the electric level fluctuates dramatically. For example, during the toggling period Tr3, the electric level of the test signal S1 exceeds the high threshold around t2 and t4, and down to the low threshold around t1 and t3, which would confuse the test result.